First half of the course is essentially CS061 material, while second half gets slightly rough due to HLSM, etc.
If you did well in CS061, you'll probably do fine here. The labs can be very unfun, but still better than CS061 labs.
The first half of the course is essentially a repeat of CS61. The second half though gets more difficult with RTL and HLSM. We were allowed a cheat sheet for the midterm and final. The labs are written in Verilog, which honestly was the toughest part of the class. Verilog is no fun and they throw it at you expecting to know a lot right off the bat. Luckily the TA for our labs provided code for us to use. Homework was taken from the textbook. It starts off easy but midway through starts to slog. Make sure to pay attention or the final won't make sense!
Labs are tedious but doable. Midterm is pretty similar to hw. However, the final was the hardest cause the grader was not liberal in terms of partial credit.
Took this with Qi Zhu. Class is extremely easy, basically just copy and paste CS61 content for the first half. In the latter half, the class is a little harder but that's only because there are more steps to get the right answer. But the steps are very straightforward and if you memorize them you can kind of figure out the answer through pure logic(e.g. how a soda vending machine should work using a finite state machine).
Almost entirely a repeat of cs061 in lecture lab was boring and unrelated but not very difficult one of the easiest classes ive ever taken
Took it with Kelly Downey, Fall 2018. Material in the first half is the easy cs61 material(gates, adders, state machines, etc.) and the last half is RTL and hlsm which is kinda rough. She allowed us to use our notes during the midterm and final. Overall the homeworks weren't that difficult, just tedious sometimes. Labs can be rough in the beginning, but once you get used to the program you have to use, the labs should only give you trouble with writing the programs in verilog. That being said always ask for help when you don't know how to do something in verilog. My TA and lab mates were a great help and made the labs super short(30-45 mins) towards the end of the quarter. I also had to do a final project with a partner during the last 2 weeks, which wasn't that bad. You have 3 projects to chose from.
Took with Downey. This class is easy, just take the time to learn Verilog in the beginning or else the labs and your mini-project are going to be extremely annoying. The lab manuals are outdated and rather unhelpful sometimes, but it may change. Your TAs are most likely not going to know Verilog - they're just there to grade. Midterm and final were open notes.
Literally CS061 but with the actual hardware.
The labs are INFURIATING, but the class itself is pretty easy. The first half is CS61 review so the midterm was insanely easy. The second midterm you should really get RTL and FSMs down, but other than that it's not so bad!
I had a good partner for the labs, vague but grading is pretty chill, final project was stressful but as long as you put in effort and know what things do youll be fine
Took with Sheriff Sadiqbatcha in Winter 2020, the midterms and final were very similar to the practice exams, so make sure you understand those. Labs were in Verilog, not terribly difficult but TAs can help with explaining. Highly recommend attending TA office hours if you have questions regarding labs as the lab manuals are not very helpful. Overall the class was not very difficult but may be different in-person as I took it remotely.
With Sheriff, really easy class. The weighting of the course was more focused on homework and lab rather than exam, due to COVID. If you put in the time you will get a good grade
The class was very easy until week 8 (Chapter 5). RTL design gets people. But the first 3-4 weeks are a repeat of CS061. Sheriff is a great instructor, and overall, you won't have too much of a hard time in the class.
This class was very easy imo. Most of the quarter was just review from CS061. The labs all amount to copy-pasting some provided Verilog code and making minor changes. My lecture section was asynchronous. I would recommend not falling behind because while the content isn't the most difficult, it's painful to try to catch up. The homework assignments are pretty tedious and fairly long, but except for the last one, they aren't too difficult.
Only hard part about the class was the final mini project because Verilog is quite confusing. Take with Sheriff and you'll be good to go. Study practice midterms he gives you. HW can be very long so start early.
Sheriff was super flexible with everything. Midterms and finals were based off homework and he even provided practice exams! They pretty much gave the code for the labs in the manual, however the final project can be tough if you don't understand what the labs. You can do well by just watching the office hour lectures where he reviews the practice exams.
I do not recommend taking this class with Matt Vaezi, I believe it is his first year teaching at UCR as of writing this and I personally do not like his teaching style at all. He makes up his own slides which aren't great either and his homework assignments are the most confusing things ever. The labs are a huge pain as well since the TA (Amir Kavousi) requires an entire list of requirements in the lab reports and gets angry pretty easily.
Our entire grade for this class came from 2 assignments, 1 midterm, 1 final, and all the labs/final project. Most of the content is a repeat of CS061, just more in-depth. If you did well in CS061 then 120A will be a breeze, if not then it might be a little challenging for you.
Took this class in spring 2021 with Matt Vaezi as the professor and Amir Kavousi as the TA. This course was a horrible experience as neither of them put any preparation towards instructing the class and expected us to figure stuff out on our own with assignments and labs. Also couldnt even stick to their own syllabus as they said there would be 4 assignments throughout the quarter and the professor only assigned 2. Very little if any communication with emails and questions. Avoid instructor if possible
Basically a repeat of the CS061 concepts, but with easier labs (no LC3). Minimal homework. Exams are easy and basically the same as the homework.
The first half of the quarter is slow and easy. He was very proud of giving us too many problems to solve for the midterm such that barely anyone finished. He also kept making announcements and had to clarify like half of the problems... During the second half of the quarter everything is tedious and he dumps like 5x the information on you compared to the first quarter. He constantly complains about having too much material to go through and expects you to watch his recordings and basically learn it on your own. Told us HW4 would be done in class but just made it due some random Sunday without telling anyone. I believe he likes teaching and is really trying to explain stuff but he's not very good at it in lecture. Labs are very disconnected from the lecture. The entire course has poor structuring and needs to be redone.
Took in Spring 2025 with Jia Chen. Just like for EE020B this class is taught through the same style of powerpoint presentation. It gets boring so I skipped all the lectures. Cheatsheet for midterm and final. Beginning is similar to CS061 and labs are in Verilog and not too closely related to lectures (though code was given to us most of the time to just copy and paste and change a little bit). Homework is graded half and half based on completion then correctness. Not much curving and grading scale is typical high weight for exams so not very forgiving if you mess up.